A signal processor transmits 5 sequential pulses, where each pulse must be chosen from modes P, Q, R, S. Mode S is an inactive override channel that cannot be used. Pulse 1 must be mode P or mode Q. The signal sequence enforces two stacked bans: mode P cannot be immediately followed by mode P, and mode Q cannot be immediately followed by mode R. Mode P can transition to Q or R; mode Q can transition to P or Q; and mode R can transition to P, Q, or R.